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Problem Set B

1 .
Suppose that we have a system with memory access time of 8 cycles. We need to add to that system a cache with 2 cycles access time. What is the smallest hit rate needed to make that cache beneficial?
2 .
Explain how there are multiple levels of abstraction in a computer and explain how at each level, complex implementation knowledge of the lower levels is not needed.
3 .
Calculate 0 1000 0001 110…0 plus 0 1000 0010 00110…0. Both are single-precision IEEE 754 representations.
4 .
We derived the equation m + (1 – p)M for average access latency when we have one cache and memory. Extend this equation to include two-level cache followed by memory.
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